A Fast Crc Implementation on Fpga Using a Pipelined Architecture for the Polynomial Division
A Fast CRC Implementation on FPGA Using a Pipelined Texture for the Polynomial Analysis Fabrice MONTEIRO, Abbas DANDACHE, Amine M’SIR,Bernard LEPLEY LICM, University of Metz, SUPELEC, Rue Edouard Belin, 57078 Metz Cedex phone: +33(0)3875473 11, fax: +33(0)387547301, email: fabrice. [email protected] org ABSTRACT The CRC hallucination challenge is a very vulgar part on telecommunication applications. The separation towards increasing basis reprimands requires further and further sofisticated utensilations. In this Nursing essay, we exhibit a rule to utensil the CRC part naturalized on a pipeline construction for the polynomial analysis.It rectifys very conducively the hurry execution, allowing basis reprimands from 1 Gbits/s to 4 Gbits/s on FPGA utensilions, according to the correlativeisation roll (8 to 32 bits).
1 INTRODUCTION The CRC (Cyclic Redundancy Checking) codes are used in a lot of telecommunication applications. They are used in the interior layers of protocols such as Ethernet, X25, FDDI and ATM (AAL5). However, on modem networks, the scarcity for increasing basis reprimands (aggravate 1 Gbit/s) is contrast the occupations on execution very eminent. Indeed, the hurry progress (conspicuous clock reprimands) due to the technological separation is weak to fit the require.Consequently, new textures must be bequeathed. Targetting the applications to an FPGA plan is an effect for this Nursing essay, as it allows low-cost artfulnesss. The unartificial and plum serial utensilation is a refined hardware utensilation of the CRC algorithm.
Unfortunatly, on an FPGA utensilation delay maximal clock abundance of 250 MHz, maximal basis reprimand is poor to 250 Mbits/s is the best instance. Conspicuous basis reprimands can solely be obtained through correlativeisation. Some correlative textures feel been contemplated in the gone-by to oration the scarcity for eminent basis throughput [ 1].The ocean gist is usually to expression the hurryily increasing area aggravatehead spaceliness fit the hurry execution. In this Nursing essay, we exhibit a correlative arrival for the polynomial analysis naturalized on a pipeline construction. The correlativeisation can be led to any roll and is solely lim- ited by the area occupation set on the artfulness. The basis throughput is approximately instantly linked to the correlativeisation roll, as the maximal clock reprimand is not very impressible to it.
2 PRINCIPLE The polynomial analysis is the primary production of the CRC applications.The serial utensilation of the analysis is pompn in likeness 1 for the instance where the polynomial divisor is G ( X ) = Go + G1. X1 + Gz. X2 + G3. X3 = 1 + X + X 3 . As involved antecedently, the basis throughput of this serial utensilation is truly low. Very eminent basis reprimands can solely be achieved delay eminent clock frequencies, which in diverge can solely be obtained using rather extravagant technological keys.
Parallelisation of basis ruleing is the ocean key to rectify the hurry execution of a tour (or way) if the clock reprimand must reocean low.Pipelining may be used as an conducive correlativeisation rule when a repeatitive rule must be applied on wide volumes of ‘data. Antecedent works feel orationed the correlativeisation gist in wide requireing computational applications, distinctly in arithmetic (eg. ) and hallucination administer coding tours (eg. [11[21[61). In the serial texture (likeness I), a new basis bit is inject on each clock cycle. The antecedent cumulated tarryder is concomitantly varied by X and disjoined by G(z) (where G(z) is the polynomial divisor).
On P Likeness I : Serial polynomial analysis for G ( X ) = 1 -tX + X 3 -7803-7057-0/01/$10. 00 02001 IEEE. 1231 successive clock cycle , P bits are injected and P successive swarming and analysiss are produced. The contiguous formula (akin to the in of likeness 1) describes the production produced on one clock cycle. 0 T = [ o o 1 !]=[n Gz 0 1 o 1 1 Go GI 0 i ] 0 3 RESULTS This texture feel been utensiled on FPGA plans of the FLEXlOKE ALTERA lineage. These plans feel their maximal clock abundance poor to 250 MHz. The texture was tested on the generating polynomials of board 1.
The effects in board 2 were obtained on FPGA plans of the FLEXlOKE ALTERA lineage.The texture tested in these ins utensils a amply productional CRC checker. The synchronisation signals to transcribe and learn basis appertainingly on input and ouput are amply utensiled. The texture was produced using Synplify 5. 3 and MaxPlus11 10. 0. The texture was tested for 3 incongruous rolls of paralelism on 6 incongruouss plummet divisor polynomials.
It can be noticed that G17(z) is used on ethernet, FDDI and AALS-ATM, spaceliness G14(z) is the plummet polynomial for the X2. 5 protocol. The clock reprimands must be compared to the eminentest abundance (250 MHz) that can be produced on FLEXlOKE plans.The “IC” manifestation media “logical cells” and is an manifestation of the area waste. The effects must be compared to those obtained in [SI. A basis reprimand of 160 Mbits/s was obtained on an ALTERA FLEXIOK plan (max. clock reprimand of 125 MHz), on a 32-bit correlative CRC runtime-configurable utensilation of the decoder, naturalized on the use of correlative combi- A pipeline construction can be bequeathed by the utensilation of P successive swarmings and analysiss.
However, to practise the clock reprimand eminent, the P productions should not be produced in a uncombined combinatorial arrest. Thus, the amounts of the P-multiplingldivising arrest must be disconnected by archives.This is the basic fancy of the pipeline construction. Each of the P correlative bits of an input must be injected in their appertaining pipeline amount. therefore, they must be injected on incongruous clock cycles. This may be produced if the bits are recent in a change-record construction and (cf. the change record route between [ d i n o ,.
.. , [douto, ... ,doutp-l] in the likeness 2, delay P = 8 in this in and G ( X ) = 1 + X + X 3 . The production produced when departure from the amount k + l to the amount k of the pipeline (k>O) is descriptive in the contiguous formula, where G ( X ) = 1 + X + X 3 as it is in likeness 2.
ith Ri,J= 0 wheni + j > p - 1. The P bits of an input are ruleed in P clock cycles. At each clock cycle, the effect of the ruleing of P bits is beneficial at the output of the pipeline construction. This effect (the tarryder of the P bits disjoined by G(z) must be cumulated in the [ROO, ROZ] ROI, record using a returning arrival, alike to the device of the serial texture of likeness 1. The cumulated tarryder at space t must be varied by X p and then disjoined by G(x). Then, the new biased tarryder hence out of the pipeline construction can be cumulated. This rule is describet in the contiguous formula.
Ro,o,ROJ,R0,Sltfl = [Ro,o,RO,l,R0,zIt * M +[Ri,o, Ri,i, Rl,z]t * T f [Do,P-l, 0,Olt natorial arrest for the polynomial analysis as exhibited in [ 11. The reach obtained on the 32-bit correlative texture is delayin 16 and 30 spaces, that is, 8 to 1. 5 spaces using the similar technology (cf. board 2). For any cabal of the artfulness parametres, the latency is alway similar to P clock cycles where P denotes the correlativeisation roll. It can be noticed that for loving a maximal polynomial divisor step, the area waste (sum of logic cells ) is approximately proportional to the correlativeisation roll of the texture.Furthermore, the effects pomp that a wide extension of the correlativeisation roll can be produced delay a moderate subside of maximal clock abundance.
The dubious route is due to the M matrix. The complication of this matrix depends on the choosen polynomial (sum and comcomposition of the non-zero conditions in the polynomial). It to-boot depends on the correlativeisation 1232 roll, but not linearly. Actually, a eminenter correlativeisation roll can manage to a close obscure matrix.